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RTL Modeling Engineer - SystemC

Mountain View, CA
Core Responsibilities:
The primary responsibility will be to develop SystemC models to substitute RTL blocks under development. You will be involved in understanding the block level specs, implement and test all the features supported by the block to come up with cycle and pin accurate SystemC model of the block well in advance of RTL. In order to test the SystemC model, you will be required to co-simulate the model with existing RTL and ensure correct behavior
Required Skills/Experience
  • SystemC knowledge/expertise
  • C/C++ coding
  • Co-simulation of Verilog and System C on one of the simulators (VCS preferred)
  • Experience with system level verification and debug (using waveforms and Verdi source level debug )
  • Excellent communication skills and demonstrate the desire to take on diverse challenges
  • Familiarity with Industry standard busses like AXI.
Desirable Skills/Experience:
  • Verilog/Systemverilog knowledge
  • Minimum BS (EE or CS) required with over 5 years of relevant experience

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